Some of the expected responsibilities of the candidate will include System level modelling of power IPs, in time and frequency domain, using the models to predict post silicon performance against key metrics. Working with designers in silicon and package and ensure power routing is done to guarantee performance Supply noise analysis at a package and board level and workin

GPU Kernel Optimization Develop and optimize low level GPU kernels to accelerate inference and training of large machine learning models. Maximize the computational efficiency and reduce execution time while ensuring model accuracy. Multi GPU and Multi Node Optimization Design and implement strategies for distributed model training and inference across multiple GPUs and n